/*************************************************************************

    p8000_8.c driver.

   Copyright Matt Knoth 2008 p8000@knothusa.net

   - This source code is released as freeware for non-commercial purposes.
   - You are free to use and redistribute this code in modified or
     unmodified form, provided you list me in the credits.
   - If you modify this source code, you must add a notice to each modified
     source file that it has been changed.
   - The author of this copywritten work reserves the right to change the
     terms of its usage and license at any time, including retroactively
   - This entire notice must remain in the source code.

**************************************************************************/ 

#include "driver.h"
#include "deprecat.h"
#include "ui.h"
#include "uimenu.h"
#include "sound/beep.h"
#include "cpu/z80/z80.h"
#include "cpu/z80/z80daisy.h"
#include "machine/z80ctc.h"
#include "machine/z80pio.h"
#include "machine/z80sio.h"
#include "machine/z80dma.h"
#include "machine/i8272_floppies.h"
#include "p8000_8.h"

extern UINT8  p8000_8_present;  // run 8bit board 

static void p8000_8_interrupt(int state);

static UINT8 p8000_8_resi_flop;
static UINT8 p8000_8_resrff_flop;
static UINT8 *mh7489[16];

static UINT8* p8000_8_RomBase;
static UINT8* p8000_8_SRamBase;
static UINT8* p8000_8_DRamBase;
extern UINT8* p8000_8_CharROM;

static UINT8 p8000_8_ctc0_0_ff;
static UINT8 p8000_8_ctc1_0_ff;
static UINT8 p8000_8_ctc1_1_ff;
static UINT8 p8000_8_ctc1_2_ff;

/*****************************************************************************************************************************************
   Keyboard handling - replace handler_ingame through local handler for full keyboard use
 ****************************************************************************************************************************************/
UINT32 handler_ingame_p8000_8(running_machine *machine, UINT32 state)
{
        return 0;
}

static void p8000_8_save_exit_cb(UINT8 param)
{
    // F3 EXIT+SAVE dialog callback
    switch(param) {
    case 3:                               // Save YES and EXIT
    case 4: mame_schedule_exit(Machine);  // Save NO  and EXIT
            break;
    }
    // chicken'd out
}

/*****************************************************************************************************************************************
   Key Handlers for emulator functions
 ****************************************************************************************************************************************/
void p8000_reset_button( void )
{    cpuinfo info;
     int i;

     p8000_8_resrff_flop = 1;                          // reset mh7489 mini-'MMU'
     p8000_8_resi_flop   = 0;                          // mark this as warmstart
     z80pio_p_w( PIO2, 0, 0x00);                       // reset resi status bit PIO2-A7
     opcode_base = opcode_arg_base = p8000_8_RomBase;  // reset mh7489 MMU
     for(i=0; i<16; i++) mh7489[i]=p8000_8_RomBase;    // reset MMU
     i8272_floppy_reset();                             // reset floppy
     z80_get_info(CPUINFO_PTR_RESET, &info);           // get Z80 reset function
     info.reset();                                     // reset Z80
}

static TIMER_CALLBACK( nmi_timer_cb )                  // brings NMI line back to 0 after NMI asserted
{
     cpunum_set_input_line(Machine, 0, INPUT_LINE_NMI, 0);
}

void p8000_nmi_button( void )
{
     cpunum_set_input_line(Machine, 0, INPUT_LINE_NMI, 1);
     timer_set(ATTOTIME_IN_MSEC(100), NULL, 0, nmi_timer_cb);
}

/****************************************************************************************************************************************
 P8000 Machine description
 ****************************************************************************************************************************************/

WRITE8_HANDLER( ctc0_tmr_out ) {

    if(data) {
       switch( offset ) {
       case 0x00:  p8000_8_ctc0_0_ff = p8000_8_ctc0_0_ff? 0 : 1; break;
       }
    }
}

WRITE8_HANDLER(  ctc1_tmr_out ) {

    if(data)  {
       switch( offset ) {
       case 0x00:  p8000_8_ctc1_0_ff = p8000_8_ctc1_0_ff? 0 : 1; break;
       case 0x01:  p8000_8_ctc1_1_ff = p8000_8_ctc1_1_ff? 0 : 1; break;
       case 0x02:  p8000_8_ctc1_2_ff = p8000_8_ctc1_2_ff? 0 : 1; break;
       }
    }
}

READ8_HANDLER( z80ctc_0x08_r )  { return z80ctc_r(CTC0, offset & 3); }
WRITE8_HANDLER( z80ctc_0x08_w ) {  z80ctc_w(CTC0, offset & 3, data); }

READ8_HANDLER(  z80pio_0x0c_r ) { return (offset & 1) ? z80pio_c_r(PIO0, (offset&2)>>1) : z80pio_d_r(PIO0, (offset&2)>>1); }
WRITE8_HANDLER( z80pio_0x0c_w ) { if (offset & 1) z80pio_c_w(PIO0, (offset&2)>>1, data); 
                                  else { z80pio_d_w(PIO0, (offset&2)>>1, data); if((offset&2) && !(data&0x80)) p8000_nmi_button(); }}

READ8_HANDLER(  z80pio_0x18_r ) { return (offset & 1) ? z80pio_c_r(PIO1, (offset&2)>>1) : z80pio_d_r(PIO1, (offset&2)>>1); }
WRITE8_HANDLER( z80pio_0x18_w ) { if (offset & 1) z80pio_c_w(PIO1, (offset&2)>>1, data); else z80pio_d_w(PIO1, (offset&2)>>1, data); }

READ8_HANDLER( z80pio_0x1c_r )  { return (offset & 1) ? z80pio_c_r(PIO2, (offset&2)>>1) : z80pio_d_r(PIO2, (offset&2)>>1); }
WRITE8_HANDLER( z80pio_0x1c_w ) { if (offset & 1) z80pio_c_w(PIO2, (offset&2)>>1, data); 
                                  else { z80pio_d_w(PIO2, (offset&2)>>1, data); 
                                         if(!(offset & 0x02)) {
                                             if( (data & 0x40)) i8272_floppy_tc();           // reset FDC when PIO2A[6] active
                                             if(!(data & 0x01)) output_set_value("lamp0",1); // FD0 on  when PIO2A[0] inactive
                                             if( (data & 0x01)) output_set_value("lamp0",0); // FD0 off when PIO2A[0]   active
                                             if(!(data & 0x02)) output_set_value("lamp1",1); // FD1 on  when PIO2A[0] inactive
                                             if( (data & 0x02)) output_set_value("lamp1",0); // FD1 off when PIO2A[0]   active
                                         }
                                  }
}

READ8_HANDLER( z80sio_0x24_r )  { return (offset & 1) ? z80sio_c_r(SIO0, (offset&2)>>1) : z80sio_d_r(SIO0, (offset&2)>>1); }
WRITE8_HANDLER( z80sio_0x24_w ) { if (offset & 1) z80sio_c_w(SIO0, (offset&2)>>1, data); else z80sio_d_w(SIO0, (offset&2)>>1, data); }

READ8_HANDLER( z80sio_0x28_r )  { return (offset & 1) ? z80sio_c_r(SIO1, (offset&2)>>1) : z80sio_d_r(SIO1, (offset&2)>>1); }
WRITE8_HANDLER( z80sio_0x28_w ) { if (offset & 1) z80sio_c_w(SIO1, (offset&2)>>1, data); else z80sio_d_w(SIO1, (offset&2)>>1, data); }

READ8_HANDLER( z80ctc_0x2c_r )  { return z80ctc_r(CTC1, offset & 3); }
WRITE8_HANDLER( z80ctc_0x2c_w ) {  z80ctc_w(CTC1, offset & 3, data); }

WRITE8_HANDLER( p8000_8_sio_0x24_transmit_cb ) { put_adm31_vt100(   offset & 0x01 , data);  }
WRITE8_HANDLER( p8000_8_sio_0x28_transmit_cb ) { put_adm31_vt100(2+(offset & 0x01), data);  }

READ8_HANDLER( mh7489_r ) {
    if(offset==4) {
       p8000_8_resrff_flop = 0;
       z80pio_p_w( PIO2, 0, (z80pio_p_r(PIO2, 0) & 0x7f));              // set resi status bit PIO2-A7
    } 
    return(0);
}

WRITE8_HANDLER( mh7489_w ) {
    cpuinfo info;
    int i;

    if(offset==4) {
       p8000_8_resrff_flop = 0;
       z80pio_p_w( PIO2, 0, (z80pio_p_r(PIO2, 0) & 0x7f));              // reset resi status bit PIO2-A7
//fprintf(stderr,"RESET resff flop\n");
    } else {           
       z80_get_info(CPUINFO_INT_REGISTER + Z80_B, &info);
       i=(0xf0 & info.i)>>4;
       switch(data) {
       case 0x0: /* preemt resi_flop observation penalty in opbase handler */
       case 0x1: mh7489[i]=p8000_8_RomBase;  break;
       case 0x2: mh7489[i]=p8000_8_SRamBase; break;
       default:  mh7489[i]=p8000_8_DRamBase; break;
       }
       opcode_memory_min=opcode_memory_max=0;
//fprintf(stderr,"mh4789[%d]=%d p: %p\n",i,data,mh7489[i]);
    }
}

static void p8000_8_dma_write_byte(offs_t offset, UINT8 data) {
	cpuintrf_push_context(0);
	program_write_byte(offset, data);
	cpuintrf_pop_context();
}

static UINT8 p8000_8_dma_read_byte(offs_t offset) {
	UINT8 result;
	cpuintrf_push_context(0);
	result = program_read_byte(offset);
	cpuintrf_pop_context();
	return result;
}

static void dma_3c_fdc_set_rdy(int status)     {  z80dma_rdy_write(0, status); }
static void dma_3c_interrupt(int status)       {  if(status) { i8272_floppy_tc(); } p8000_8_interrupt(status); }
static void pio2a_1e_fdc_int_sense(int status) {  z80pio_p_w(PIO2, 1, (status)? 0x10 : 0x00); }

READ8_HANDLER( dummy_io1_r )  { fprintf(stderr,"READ : port: [0x10+%02x]\n",offset); return(0); }
WRITE8_HANDLER( dummy_io1_w ) { fprintf(stderr,"WRITE: port: [0x10+%02x]=%02x\n",offset,data); }
READ8_HANDLER( dummy_io4_r )  { fprintf(stderr,"READ : port: [0x30+%02x]\n",offset); return(0); }
WRITE8_HANDLER( dummy_io4_w ) { fprintf(stderr,"WRITE: port: [0x30+%02x]=%02x\n",offset,data); }
READ8_HANDLER( dummy_io5_r )  { fprintf(stderr,"READ : port: [0x3d+%02x]\n",offset); return(0); }
WRITE8_HANDLER( dummy_io5_w ) { fprintf(stderr,"WRITE: port: [0x3d+%02x]=%02x\n",offset,data); }

READ8_HANDLER( p8000_8_ram_rom_acc_r ) { 
  UINT8 *membase;
  UINT8 resval;
  
//fprintf(stderr,"RD: %x\n",offset);
  membase=mh7489[0xf & (offset>>12)];
       if(membase==p8000_8_DRamBase) resval=*(membase+(offset & 0xffff)); 
  else if(membase==p8000_8_SRamBase) resval=*(membase+(offset & 0x07ff)); //fprintf(stderr,"RD[%04x]==%02x p: %p\n",offset,resval,membase); }
  else if(membase==p8000_8_RomBase ) resval=*(membase+(offset & 0x1fff)); 
  else                               resval=0;

  return(resval);
}

WRITE8_HANDLER( p8000_8_ram_rom_acc_w ) { 
  UINT8 *membase;

  membase=mh7489[0xf & (offset>>12)];
//fprintf(stderr,"WR: %x %x p: %p mmuidx: %x\n",offset,data,membase,0xf & (offset>>12));
       if(membase==p8000_8_DRamBase) membase[offset & 0xffff]=data;
  else if(membase==p8000_8_SRamBase) membase[offset & 0x07ff]=data; // fprintf(stderr,"WR[%04x]=%02x p: %p\n",offset,data,membase); }
}

static ADDRESS_MAP_START( p8000_8_memmap, ADDRESS_SPACE_PROGRAM, 8 )
      ADDRESS_MAP_FLAGS( AMEF_UNMAP(1) )
      AM_RANGE(0x00000, 0x0ffff) AM_READWRITE(p8000_8_ram_rom_acc_r,p8000_8_ram_rom_acc_w) AM_BASE(&p8000_8_DRamBase)                  /* DRAM */
      AM_RANGE(0x00000, 0x01fff) AM_READWRITE(p8000_8_ram_rom_acc_r,p8000_8_ram_rom_acc_w) AM_REGION(REGION_CPU1,0);                   /* EPROMS */
ADDRESS_MAP_END

static ADDRESS_MAP_START( p8000_8_portmap, ADDRESS_SPACE_IO, 8 )
      ADDRESS_MAP_FLAGS( AMEF_ABITS(8) | AMEF_UNMAP(1) )
      AM_RANGE(0x00, 0x07) AM_READWRITE(mh7489_r,mh7489_w )
      AM_RANGE(0x08, 0x0b) AM_READWRITE(z80ctc_0x08_r,z80ctc_0x08_w)
      AM_RANGE(0x0c, 0x0f) AM_READWRITE(z80pio_0x0c_r,z80pio_0x0c_w)
      AM_RANGE(0x10, 0x17) AM_READWRITE( dummy_io1_r,  dummy_io1_w )
      AM_RANGE(0x18, 0x1b) AM_READWRITE(z80pio_0x18_r,z80pio_0x18_w)
      AM_RANGE(0x1c, 0x1f) AM_READWRITE(z80pio_0x1c_r,z80pio_0x1c_w)
      AM_RANGE(0x20, 0x23) AM_READWRITE( i8272_fdc_r, i8272_fdc_w  )
      AM_RANGE(0x24, 0x27) AM_READWRITE(z80sio_0x24_r,z80sio_0x24_w)
      AM_RANGE(0x28, 0x2b) AM_READWRITE(z80sio_0x28_r,z80sio_0x28_w)
      AM_RANGE(0x2c, 0x2f) AM_READWRITE(z80ctc_0x2c_r,z80ctc_0x2c_w)
      AM_RANGE(0x30, 0x3b) AM_READWRITE( dummy_io4_r, dummy_io4_w  )
      AM_RANGE(0x3c, 0x3c) AM_READWRITE( z80dma_0_r,  z80dma_0_w   )
      AM_RANGE(0x3d, 0xff) AM_READWRITE( dummy_io5_r, dummy_io5_w  )
ADDRESS_MAP_END

/*************************************
 *
 *  Machine "start"
 *
 *************************************/

static const z80pio_interface p8000_8_0x0c_pio_intf = {
        p8000_8_interrupt,     /* interrupt handler */
        0,                     /* portA ready active callback */
        0                      /* portB ready active callback */
};

static const z80pio_interface p8000_8_0x18_pio_intf = {
        p8000_8_interrupt,     /* interrupt handler */
        0,                     /* portA ready active callback */
        0                      /* portB ready active callback */
};

static const z80pio_interface p8000_8_0x1c_pio_intf = {
        p8000_8_interrupt,     /* interrupt handler */
        0,                     /* portA ready active callback */
        0                      /* portB ready active callback */
};

static z80ctc_interface p8000_8_0x08_ctc_intf = {
	1229000,          /* 1.22MHz clock */
        0,                /* timer disables */
        p8000_8_interrupt,/* interrupt handler */
        ctc0_tmr_out,     /* ZC/TO0 callback */
        0,                /* ZC/TO1 callback */
        0                 /* ZC/TO2 callback */
};

static z80ctc_interface p8000_8_0x2c_ctc_intf = {
	1229000,          /* 1.22MHz clock */
	0,                /* timer disables */
	p8000_8_interrupt,/* interrupt handler */
	ctc0_tmr_out,     /* ZC/TO0 callback */
	ctc0_tmr_out,     /* ZC/TO1 callback */
	ctc0_tmr_out      /* ZC/TO2 callback */
};

static z80sio_interface p8000_8_0x24_sio_intf =
{
	9600,                        /* 9.6kBaud default */
	p8000_8_interrupt,           /* interrupt handler */
	0,			     /* DTR changed handler */
	0,		             /* RTS changed handler */
	0,  	                     /* BREAK changed handler */
	p8000_8_sio_0x24_transmit_cb /* transmit handler */
};

static z80sio_interface p8000_8_0x28_sio_intf =
{
        9600,                        /* 9.6kBaud default */
        p8000_8_interrupt,           /* interrupt handler */
        0,                           /* DTR changed handler */
        0,                           /* RTS changed handler */
        0,                           /* BREAK changed handler */
        p8000_8_sio_0x28_transmit_cb /* transmit handler */
};

static const struct z80dma_interface p8000_8_dma_intf =
{
	0,                        /* cpu0 */
	4000000,                  /* 4MHz */
	p8000_8_dma_read_byte,    /* mem read  */
	p8000_8_dma_write_byte,   /* mem write */
	i8272_fdc_disk_r,         /* port A read  accessor */
        i8272_fdc_disk_w,         /* port A write accessor */
        i8272_fdc_disk_r,         /* port B read  accessor */
        i8272_fdc_disk_w,         /* port B write accessor */
        dma_3c_interrupt          /* interrupt handler */
};

static const i8272_floppy_intf p8000_8_floppy_intf =
{
        pio2a_1e_fdc_int_sense,  // void (*interrupt)(int state); /* interrupt issued */
        dma_3c_fdc_set_rdy       // void (*dma_drq)(int state);   /* dma data request */
};

static OPBASE_HANDLER( p8000_8_opbase_handler ) {
     UINT8 idx = 0xf & (address>>12);
     opcode_base = opcode_arg_base = mh7489[idx];
     opcode_memory_min=opcode_memory_max=idx<<12; 
     if(opcode_base==p8000_8_DRamBase) { opcode_memory_max|=0x0fff; opcode_mask=0xffff; } else
     if(opcode_base==p8000_8_RomBase)  { opcode_memory_max|=0x0fff; opcode_mask=0x1fff; } else
                    /* SRamBase */     { opcode_memory_max|=0x07ff; opcode_mask=0x07ff; }
     return ~0;
}

MACHINE_START( p8000_8 ) {  // cold start
      int i;

      // replace original ingame handler with own to use full keyboard */
      ui_set_handler_ingame( handler_ingame_p8000_8, 0 );
      uimenu_set_on_exit_callback(p8000_8_save_exit_cb);     // exit dialog upon F3

      p8000_8_present=1;          // 8bit board running

      p8000_8_resi_flop   = 1;    // pwr on coldstart
      p8000_8_resrff_flop = 1;    // reset has been seen

      /* set up memory */
      p8000_8_RomBase = (UINT8 *)memory_region(REGION_CPU1);
      p8000_8_SRamBase = (UINT8 *)auto_malloc(0x0800);
      p8000_8_CharROM = (UINT8 *)memory_region(REGION_PROMS);
      state_save_register_global_pointer(p8000_8_SRamBase,0x800);
      state_save_register_global_pointer(p8000_8_DRamBase,0x10000);

      // initialize 'MMU'
      for(i=0; i<16; i++) mh7489[i]=p8000_8_RomBase;

      memory_set_opbase_handler(0, p8000_8_opbase_handler);
      opcode_base = opcode_arg_base = p8000_8_RomBase;

      memory_install_read8_handler( 0, ADDRESS_SPACE_PROGRAM, 0x0000, 0xffff, 0xffff, 0x0000, p8000_8_ram_rom_acc_r);
      memory_install_write8_handler(0, ADDRESS_SPACE_PROGRAM, 0x0000, 0xffff, 0xffff, 0x0000, p8000_8_ram_rom_acc_w);

      z80pio_init(PIO0, &p8000_8_0x0c_pio_intf);
      z80pio_reset(PIO0);
      z80pio_init(PIO1, &p8000_8_0x18_pio_intf);
      z80pio_reset(PIO1);
      z80pio_init(PIO2, &p8000_8_0x1c_pio_intf);
      z80pio_reset(PIO2);
      z80ctc_init(CTC0, &p8000_8_0x08_ctc_intf);
      z80ctc_init(CTC1, &p8000_8_0x2c_ctc_intf);
      z80sio_init(SIO0, &p8000_8_0x24_sio_intf);
      z80sio_set_dcd(SIO0, 0, 1);
      z80sio_set_cts(SIO0, 0, 1);
      z80sio_set_dcd(SIO0, 1, 1);
      z80sio_set_cts(SIO0, 1, 1);
      z80sio_init(SIO1, &p8000_8_0x28_sio_intf);
      z80sio_set_dcd(SIO1, 0, 1);
      z80sio_set_cts(SIO1, 0, 1);
      z80sio_set_dcd(SIO1, 1, 1);
      z80sio_set_cts(SIO1, 1, 1);

      z80dma_init(1);
      z80dma_config(0, &p8000_8_dma_intf);

      init_floppy_menu(0);
      i8272_floppy_init( &p8000_8_floppy_intf );
}

MACHINE_RESET( p8000_8 )
{
        p8000_8_ctc0_0_ff=0;
        p8000_8_ctc1_0_ff=0;
        p8000_8_ctc1_1_ff=0;
        p8000_8_ctc1_2_ff=0;

        z80pio_p_w(PIO0, 0, 0xff);           // set PIO0 A:= 0xff
        z80pio_p_w(PIO2, 0, 0xff);           // set Bit7 - hard reset state
        z80dma_reset(DMA);
}

/*************************************
 *
 *  Machine drivers
 *
 *************************************/

static MACHINE_DRIVER_START( p8000_8 )
      MDRV_CPU_ADD(Z80, 4000000 )
      MDRV_CPU_PROGRAM_MAP(p8000_8_memmap,0)
      MDRV_CPU_IO_MAP(p8000_8_portmap,0)
      MDRV_CPU_CONFIG(p8000_8_daisy_chain)

      MDRV_MACHINE_START( p8000_8 )
      MDRV_MACHINE_RESET( p8000_8 )

      MDRV_SOUND_ADD(BEEP, 1000);

      /* video hardware */
      MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
      MDRV_SCREEN_ADD("main", 0)
      MDRV_SCREEN_FORMAT(BITMAP_FORMAT_RGB15)
      MDRV_SCREEN_SIZE(640,480)
      MDRV_SCREEN_VISIBLE_AREA(0,639, 0,479)
      MDRV_SCREEN_REFRESH_RATE(15)

      MDRV_VIDEO_START( p8000_8 )
      MDRV_VIDEO_UPDATE( p8000_8 )

MACHINE_DRIVER_END

/*************************************
 *
 *  Input ports
 *
 *************************************/

static INPUT_PORTS_START( p8000_8 )
INPUT_PORTS_END


/*************************************
 *
 *  Daisy Chain
 *
 *************************************/

const struct z80_irq_daisy_chain p8000_8_daisy_chain[] = {

        { z80dma_reset, z80dma_irq_state, z80dma_irq_ack, z80dma_irq_reti, 0 }, /* DMA  number 0x3c */
        { z80pio_reset, z80pio_irq_state, z80pio_irq_ack, z80pio_irq_reti, 2 }, /* PIO2 number 0x1c */
	{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 0 }, /* CTC0 number 0x08 */
	{ z80sio_reset, z80sio_irq_state, z80sio_irq_ack, z80sio_irq_reti, 0 }, /* SIO0 number 0x24 */
	{ z80sio_reset, z80sio_irq_state, z80sio_irq_ack, z80sio_irq_reti, 1 }, /* SIO1 number 0x28 */
        { z80pio_reset, z80pio_irq_state, z80pio_irq_ack, z80pio_irq_reti, 0 }, /* PIO0 number 0x0c */
        { z80pio_reset, z80pio_irq_state, z80pio_irq_ack, z80pio_irq_reti, 1 }, /* PIO1 number 0x18 */
	{ z80ctc_reset, z80ctc_irq_state, z80ctc_irq_ack, z80ctc_irq_reti, 1 }, /* CTC1 number 0x2c */
        { 0, 0, 0, 0, -1 }              /* end mark */
};

static void p8000_8_interrupt(int state)
{
	cpunum_set_input_line(Machine, 0, 0, state);
}

/*************************************
 *
 *  ROM definitions
 *
 *************************************/

ROM_START( p8000_8 )
      ROM_REGION( 0x2000, REGION_CPU1, 0 )
      ROM_LOAD( "mon8_1_3.1",	0x0000, 0x1000, CRC(ad1bb118))
      ROM_LOAD( "mon8_2_3.1",	0x1000, 0x1000, CRC(daced7c2))

#ifdef NEVER
      ROM_LOAD( "mon8_1_3.0",	0x0000, 0x1000, CRC(5945115c))
      ROM_LOAD( "mon8_2_3.0",	0x1000, 0x1000, CRC(a6fa0683))
      ROM_LOAD( "mon8_1_3.1_nur8bit",	0x0000, 0x1000, CRC(5945115c))
      ROM_LOAD( "mon8_2_3.1_nur8bit",	0x1000, 0x1000, CRC(060bb1b7))
#endif

      ROM_REGION( 0x1000, REGION_PROMS, 0 )
      ROM_LOAD( "p8t_zs",         0x0000, 0x0800, CRC(f9321251))
      ROM_LOAD( "p8tdzs.2",       0x0800, 0x0800, CRC(32736503))
ROM_END

/*************************************
 *
 *  Game drivers
 *
 *************************************/

GAME( 1989, p8000_8, 0, p8000_8, p8000_8, 0, ROT0, "EAW electronic Treptow", "P8000 8bit Board Emulation", 0 ) 

